· AI accelerator subsystems requiring BF16 vector computation for inference and training kernels. Data

Semiconductor IP / AI Accelerator (Artificial Intelligence and Machine Learning), System-on-Chip (SoC) design, FPGA prototyping and emulation, and academic research and education in computer architecture.

• IP Name :

  VPU (Vector Processing Unit)

• Provider :

  Scalable Architecture Lab, Sungkyunkwan University

• FPGA Device :

  AMD/Xilinx Versal HBM XCVH1582-VSVA3697-2MP-e-S (VHK158 Evaluation Board)

• Foundry :

  N/A

• Technology :

  FPGA

· Synthesizable RTL source code (SystemVerilog) including the top-level wrapper, decoder, controller, source-operand port, execution unit with 16 vector lanes and a reduction unit, write-back unit, per-operation BF16 floating-point wrappers, and common FIFO and SRAM models. Parameter package (VPU_PKG) defining datapath, instruction, and SPM configuration. Design and simulation file lists for tool integration. Xilinx IP generation script (Tcl) that instantiates the Floating-Point Operator v7.1 cores for add/sub, compare, multiply, divide, square root, exponential, and logarithm. Vivado simulation and synthesis automation scripts (Tcl and shell) with a timing constraint file, producing timing-summary and resource-utilization reports. SystemVerilog testbench with DPI-C support, a C golden reference model based on the Xilinx bit-accurate floating-point C model, and Python test-vector generators. GitHub Actions continuous-integration workflows for automated simulation and synthesis. Instruction set documentation and digital datasheet describing the architecture, interface signals, and functional behavior.

· Verified at the IP level through Vivado RTL simulation using a self-checking SystemVerilog testbench with file-based test vectors, where results are compared element by element against a C golden reference model built on the Xilinx bit-accurate floating-point C model. Verification covers instruction decoding, request and response handshake, SPM read and write port transactions, per-lane BF16 arithmetic, and cross-lane reduction operations. Vivado synthesis is performed automatically with timing and resource-utilization reporting, and both simulation and synthesis run on every pull request and on a nightly schedule through a continuous-integration flow. Standalone FPGA implementation and on-board bring-up have not been performed, as the VPU is intended to be integrated with an NPU subsystem for FPGA prototyping. Silicon validation has not been performed.

Available now. Version 1.0.0, released as synthesizable RTL source code.

· The VPU removes the need for a separate vector register file by addressing all operands directly in the on-chip Scratchpad Memory, which simplifies the datapath and reduces data-movement overhead for data-parallel AI kernels. Its modular block structure of decoder, controller, source-operand port, execution unit, and write-back unit provides a clear separation between host-side instruction issue and SPM-side data movement, making the IP easy to analyze, verify, and integrate. Three independent SPM read ports allow up to three source operands to be fetched concurrently, and operand FIFOs decouple SPM read latency from execution timing. The BF16 arithmetic units are built on Xilinx Floating-Point Operator v7.1 IP cores, so numerical behavior is bit-accurate against the vendor C model and the design maps efficiently onto FPGA DSP and logic resources. A single 128-bit instruction format covers element-wise arithmetic, unary math such as exponential, logarithm, square root and reciprocal square root, and cross-lane reduction, so a wide range of AI kernels can be expressed without additional hardware. The simple valid/ready request interface and req/ack SRAM interface impose minimal integration constraints on the host and memory subsystem. A continuous-integration flow runs Vivado simulation and synthesis automatically on every pull request and nightly, keeping the RTL in a verified and synthesizable state.