Figure 1 shows the functional block diagram of the frequency divider. It receives two complementary CMOS-level inputs, WCLK and WCLKB. When DIVEN is high, the block generates four-phase quadrature CMOS-level outputs: ICLK, QCLK, IBCLK, and QBCLK. When AFEN is high, a delayed version of ICLK, labeled ICLK_AF, is also provided. VLDO denotes the supply voltage of the block.
Feature
· • Digital buffer having four inputs and four outputs.
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• Output frequency up to 11 GHz.
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• Supply voltage: 0.9 V to 1.1 V
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• Industrial temperature range: –40°C to 125°C
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• Input capacitance: 5 fF for WCLK, WCLKB
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• Core area: 5.2 um x 2.82 um
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• Power Consumption (NN corner)
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- 50.3 uW at 1 GHz
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- 633.4 uW at 13 GHz
Application
· • PLL
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• Clock distribution
Business Area
Frequency Synthesizer for Memory, Automotive, Communication Area
Category
Analog & Mixed Signal > Analog Subsystems
Tech Specs
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IP Name :
Frequency Divider
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Provider :
SeongHwan Cho
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Foundry :
SAMSUNG
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Technology :
28nm
Deliverables
· Schematic netlist & testbench
Validation Status
· Simulation-proven
Availability
Samsung 28nm Only
