Feature
· • Bandwidth and Resolution Reconfigurable NS-SAR ADC with 200 MHz sampling rate
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– Supports mode switching between SAR (5-bit, BW: 100 MHz) and NS-SAR (8-bit, BW: 8 MHz)
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• Reconfigurable Noise-Shaping Integrator
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– Mode-selectable passive integration for first-order noise shaping with NTF of 1−0.8z⁻¹
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• High-Speed Operation with Energy Efficiency
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– 200 MS/s sampling clock with 5-bit CDAC in both modes
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– Set-and-down switching scheme for reduced switching energy
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• Compact and Scalable SAR ADC Architecture
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– 5-bit metal-oxide-metal (MOM) CDAC, dynamic comparator, bootstrapped input switch
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• Dynamic Performances
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– SNDR/SFDR: 31 dB / 42.5 dB (SAR), 50 dB / 50.7 dB (NS-SAR)
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• Optimized for PIM Systems
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– Suitable for both inference and training modes with a single ADC core
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• Area and Power Efficiency
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– Core area: 0.0035 mm² in 28 nm CMOS
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– Total power: 183.2 µW (84 µW for ADC, 99.2 µW for control logic)
Application
· Process-In-Memory Application (ex. Output interface between analog computing-based CNN layer and dig
Business Area
Automotive Radar or LiDAR system, Memory system
Deliverables
· Schematic netlist & layout & testbench
