• The proposed processing-in-memory macro is a monolithic, low-power, high-density analog PIM solution fabricated in 28 nm CMOS technology. It features a 4T1C dual-port DRAM cell (DPC) that physically separates the refresh and MAC (multiply-and-accumulate) ports, enabling simultaneous refresh and computation (SMR)—a breakthrough that addresses the refresh bottleneck of prior DRAM-PIM designs. This dual-port structure allows the refresh cycle to proceed independently without stalling MAC operations, significantly improving throughput by 27.5%.
The cell is designed with both MOS and MOM capacitors to ensure sufficient data retention time (DRT), while the refresh logic uses a dedicated read bitline and write bitline for non-destructive restoration.