IP 검색 Category Analog & Mixed Signal(14) Memory Controller & PHY(0) Memory & Logic Library(9) Interface Controller & PHY(0) Processor Solutions(3) Arithmetic & Mathematic IP(1) Peripheral(1) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(1) Other(83) Verification IP(9) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 119건 현재 페이지 11/30 DMA (차세대지능형반도체사업단) · DRAM Access 없이 IP간의 데이터 전송 지원 장치 2024-08-29 DQS buffer (차세대지능형반도체사업단) · Write/read strobe signal 를 위한 buffer 2024-08-29 DRAM MAC Processing Unit • This MAC (Multiplication and Accumulation) circuit performs computations on 64 pairs of 8-bit inputs and 8-bit weights. The input values are provided in digital form, and the intermediate computation results are stored as analog voltage levels through capacitive coupling. Once the final analog voltage generation is complete, the result is converted back into an 8-bit digital value using an Analog-to-Digital Converter (ADC), thus completing the computation process. To enable parallel multiplication and accumulation of the 64 input-weight pairs, the MAC circuit is composed of 64 "unit multipliers" connected along a long accumulation line. Each unit multiplier multiplies the same 8-bit input and 8-bit weight. In each unit, the weight is fixed, and the input is streamed in a bit-serial manner, two bits at a time, to perform the multiplication. The multiplication result drives an internal capacitor driver within the multiplier. If the result is 1, the driver induces a voltage change on the accumulation line via capacitive coupling; if the result is 0, no voltage change occurs. This mechanism generates an analog voltage that reflects the accumulated result. To support floating-point computation characteristics, the circuit first determines the maximum exponent among the 64 input-weight pairs. Each unit multiplier receives the exponent difference between its own input-weight pair and this maximum exponent. Based on the received exponent difference, each unit adjusts the timing of input bit streaming to reflect the relative exponent alignment among the floating-point numbers. As a result, the MAC circuit generates an analog voltage in the range of 426 mV to 973 mV, and the ADC quantizes this voltage range into an 8-bit digital output. 2025-07-04 DRAM PIM cell & Array • The proposed processing-in-memory macro is a monolithic, low-power, high-density analog PIM solution fabricated in 28 nm CMOS technology. It features a 4T1C dual-port DRAM cell (DPC) that physically separates the refresh and MAC (multiply-and-accumulate) ports, enabling simultaneous refresh and computation (SMR)—a breakthrough that addresses the refresh bottleneck of prior DRAM-PIM designs. This dual-port structure allows the refresh cycle to proceed independently without stalling MAC operations, significantly improving throughput by 27.5%. The cell is designed with both MOS and MOM capacitors to ensure sufficient data retention time (DRT), while the refresh logic uses a dedicated read bitline and write bitline for non-destructive restoration. 2025-07-04 처음으로 이전페이지 6 7 8 9 10 11 12 13 14 15 >다음페이지 마지막으로
