IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(23) Processor Solutions(39) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 140건 현재 페이지 12/35 최신 순 오래된 순 Input Clock Buffer This digital buffer takes CMOS level input and generates CMOS level output. It achieves high power efficiency, low rise-fall skew, and moderate noise level. Figure 1 shows a functional block diagram of the buffer. Four inputs (in0 ~ in3) are respectively buffered. 2025-06-24 Frequency Divider Figure 1 shows the functional block diagram of the frequency divider. It receives two complementary CMOS-level inputs, WCLK and WCLKB. When DIVEN is high, the block generates four-phase quadrature CMOS-level outputs: ICLK, QCLK, IBCLK, and QBCLK. When AFEN is high, a delayed version of ICLK, labeled ICLK_AF, is also provided. VLDO denotes the supply voltage of the block. 2025-06-24 Write-with-Feedback Circuit The Write-with-Feedback Circuit is an analog amplifier IP designed for use in read and write operations of analog memory systems. During these operations, a source follower typically connected to the back end of the storage capacitor introduces a threshold voltage (Vth) drop, resulting in a mismatch between the written and read voltage levels. This mismatch can cause distortion in the read-out value, degrading memory accuracy. To address this issue, the amplifier enables a write-with-feedback loop that virtually shorts the write input and the memory’s output node. By enforcing this virtual short condition, the amplifier compensates for the Vth drop during the write operation, ensuring that the intended voltage is properly stored in the analog memory and accurately retrieved during the read phase. The amplifier is implemented using a 5-transistor operational amplifier (5-tr opamp) topology, in Samsung’s 28 nm LPP CMOS process using analog low-Vth (anglvt) devices. 2025-06-24 Capacitive Memory Unit-Cell The analog memory stores data using a 1T1C(SWR , Cmem) structure, similar to that of DRAM. To prevent data destruction during read operations, the write and read ports are physically separated. A storage capacitor is placed between these ports, and a source-follower buffer is used to sense the stored voltage without disturbing it. The source-follower consists of an NMOS(M1) input transistor and a current source(M2) biased by an analog voltage(VB). To enhance throughput by 3×, three read switches(SRD0, SRD1, SRD2) are connected to the output of the source-follower. The circuit operates from a 0.9 V to 1.1 V supply and supports an input voltage range of 0.2 V to 0.8 V. It functions reliably over a –20 °C to 85 °C temperature range and can be effectively used in energy-efficient analog in-memory computing (IMC) applications. 2025-06-24 처음으로 이전페이지 7 8 9 10 11 12 13 14 15 16 >다음페이지 마지막으로
