IP 검색 Category Analog & Mixed Signal(14) Memory Controller & PHY(0) Memory & Logic Library(9) Interface Controller & PHY(0) Processor Solutions(3) Arithmetic & Mathematic IP(1) Peripheral(1) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(1) Other(83) Verification IP(9) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 119건 현재 페이지 8/30 CML Driver The CML driver drives two pairs differential CMOS level inputs (inIp & inIn, inQp & inQn) to two pairs of differential current-mode logic outputs (Ioutp & Ioutn, Qoutp & Qoutn) with minimum skew for high speed signal distribution. The CML driver is specifically designed for a clock distribution network for high speed signaling. A bias current is necessary to bias the current sources in the CML driver. The biasing circuitry can be amortized over multiple drivers to minimize the overhead. The device operates from 0.9-V to 1.1-V supply environment and is characterized from –40°C to 125°C. The CML driver employs a fully differential structure in order to maximize the rejection capabilities against common-mode noise and power supply noise. The CML driver has been experimentally verified through its application in LPDDR5 DRAM interface. 2025-06-24 CML-to-CMOS The CML2CMOS is a compact converter IP that translates differential current-mode logic (CML) clock signals into full-swing CMOS levels. Fabricated in a 28 nm CMOS process, it supports output clock frequencies up to 1.87 GHz while consuming less than 0.5 mW. The IP receives differential CML inputs and converts them into CMOS logic outputs using a two-stage architecture. Each stage consists of a current-steering differential pair that performs differential-to-single-ended conversion and is followed by a CMOS inverter buffer. The same structure is duplicated across phases to produce four-phase outputs: ICLK, IBCLK, QCLK, and QBCLK. This ensures matched delay paths and balanced timing across all phases. The converter supports basic bias-based configurability through an external analog control voltage, “VB”, that sets the tail current of the differential pair. This mechanism allows limited tuning of delay and power characteristics to adapt to different operating conditions. Designed for robustness and compactness, the CML2CMOS block is suitable for clock signal reception and level translation in differential clock distribution paths such as memory interfaces, SerDes, and other high-speed clocking architectures. 2025-06-24 CML-to-CMOS (차세대지능형반도체사업단) · CML 신호 범위를 full range 로 확장 (CMOS) 시키기 위한 block 2024-08-29 Current-mode Driver for 50Gb/s SerDes transmitter (차세대지능형반도체사업단) · Chip-to-Chip interface system을 위한 current-mode driver 2024-08-29 처음으로 이전페이지 3 4 5 6 7 8 9 10 11 12 >다음페이지 마지막으로
