IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(23) Processor Solutions(39) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 140건 현재 페이지 8/35 최신 순 오래된 순 DRAM MAC Processing Unit • This MAC (Multiplication and Accumulation) circuit performs computations on 64 pairs of 8-bit inputs and 8-bit weights. The input values are provided in digital form, and the intermediate computation results are stored as analog voltage levels through capacitive coupling. Once the final analog voltage generation is complete, the result is converted back into an 8-bit digital value using an Analog-to-Digital Converter (ADC), thus completing the computation process. To enable parallel multiplication and accumulation of the 64 input-weight pairs, the MAC circuit is composed of 64 "unit multipliers" connected along a long accumulation line. Each unit multiplier multiplies the same 8-bit input and 8-bit weight. In each unit, the weight is fixed, and the input is streamed in a bit-serial manner, two bits at a time, to perform the multiplication. The multiplication result drives an internal capacitor driver within the multiplier. If the result is 1, the driver induces a voltage change on the accumulation line via capacitive coupling; if the result is 0, no voltage change occurs. This mechanism generates an analog voltage that reflects the accumulated result. To support floating-point computation characteristics, the circuit first determines the maximum exponent among the 64 input-weight pairs. Each unit multiplier receives the exponent difference between its own input-weight pair and this maximum exponent. Based on the received exponent difference, each unit adjusts the timing of input bit streaming to reflect the relative exponent alignment among the floating-point numbers. As a result, the MAC circuit generates an analog voltage in the range of 426 mV to 973 mV, and the ADC quantizes this voltage range into an 8-bit digital output. 2025-07-04 DRAM PIM cell & Array • The proposed processing-in-memory macro is a monolithic, low-power, high-density analog PIM solution fabricated in 28 nm CMOS technology. It features a 4T1C dual-port DRAM cell (DPC) that physically separates the refresh and MAC (multiply-and-accumulate) ports, enabling simultaneous refresh and computation (SMR)—a breakthrough that addresses the refresh bottleneck of prior DRAM-PIM designs. This dual-port structure allows the refresh cycle to proceed independently without stalling MAC operations, significantly improving throughput by 27.5%. The cell is designed with both MOS and MOM capacitors to ensure sufficient data retention time (DRT), while the refresh logic uses a dedicated read bitline and write bitline for non-destructive restoration. 2025-07-04 Level Shifter • The proposed level shifter, named the diode-connected cross coupled pFET level shifter with staked split-input inverter (DCPLS-SSI) is a wide-range voltage conversion and energy-efficient solution for DRAM voltage conversion in 28 nm CMOS technology. The proposed level shifter can mitigate the current contention by using diode-connected cross coupled pFET structure, which enables wide-range voltage conversion. In addition, the stacked split-input inverter can reduce the short-circuit current of output inverter, which enable energy-efficient operation. 2025-07-04 I/O Sense Amplifier • The proposed sense amplifier, named the Static Current-Free Pre-Sensing IO Sense Amplifier (SCFP-IOSA), is a high-speed, low-power sensing solution for DRAM global I/O in 28 nm CMOS technology. It employs a direct input transfer architecture using a single coupling capacitor (CC) and introduces a static current-free pre-sensing technique to minimize offset voltage (VOS), area, and energy overhead. Unlike conventional offset cancellation (OC)-based I/O sense amplifiers, which suffer from input voltage attenuation, large area due to dual CCs, and static current during sensing, SCFP-IOSA eliminates attenuation by directly transferring the input differential voltage (ΔVGIO) and avoids static current using exponential RC pre-amplification. The proposed design separates ΔVGIO generation and sensing by GIO switches, allowing simultaneous offset cancellation and input development. This reduces sensing time overhead and enables a fast sensing time of 3.75 ns, with 2.15 μW power consumption, and 10.28 μm² area, achieving 3× lower σVOS, 2.9× lower power, and 4.46× smaller area compared to state-of-the-art OC-IOSA. Moreover, it shows robust sensing yield even in noisy conditions, and maintains performance at low supply voltages. These characteristics make SCFP-IOSA highly suitable for next-generation low-voltage, high-density DRAM applications, particularly in 1Ynm-class or beyond. 2025-07-04 처음으로 이전페이지 3 4 5 6 7 8 9 10 11 12 >다음페이지 마지막으로
