IP 검색 Category Analog & Mixed Signal(14) Memory Controller & PHY(0) Memory & Logic Library(9) Interface Controller & PHY(0) Processor Solutions(3) Arithmetic & Mathematic IP(1) Peripheral(1) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(1) Other(83) Verification IP(9) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 119건 현재 페이지 4/30 64:4 serializer for 50Gb/s SerDes transmitter (차세대지능형반도체사업단) · Chip-to-Chip interface system을 위한 64:4 serializer 2024-08-29 64bit parallel PRBS generator (차세대지능형반도체사업단) · Chip-to-Chip interface system을 위한 64bit parallel PRBS generator 2024-08-29 Adaptive Gradient Clipping for Quantization Aware Training (차세대지능형반도체사업단) · 양자화 후 학습(Quantization-Aware Training) 시, 레이어에 적응적인 Gradient Clipping을 하기 위한 유닛(IP) 2024-08-29 Address Buffer • The row decoder is designed to process a 9-bit address input, selecting one out of 512 rows. To minimize decoding latency and area overhead, the address is divided across multiple logic stages, enabling efficient one-hot decoding. This hierarchical structure reduces fan-out and simplifies signal routing, which is critical for large-scale integration. Addressing optimization is particularly important in DRAM-PIM architectures, where frequent switching and tight timing constraints demand fast and energy-efficient row selection. By optimizing the address path, the decoder ensures reliable wordline activation across subarrays without unnecessary delay or power loss, directly contributing to the overall performance and scalability of the system. 2025-07-04 처음으로 이전페이지 1 2 3 4 5 6 7 8 9 10 >다음페이지 마지막으로
