IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(23) Processor Solutions(39) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 140건 현재 페이지 7/35 최신 순 오래된 순 DRAM Refresh Circuit • The Adaptive Refresh Tracking (ART) mechanism dynamically adjusts refresh timing based on real-time retention behavior, minimizing unnecessary refresh operations and power overhead. ART utilizes two types of replica eDRAM cells: a Static Replica DPC (SRDPC) and a Dynamic Replica DPC (DRDPC). The SRDPC is isolated from leakage effects and provides a stable voltage reference, while the DRDPC mimics the leakage characteristics of real cells in the array. By comparing the wordline accumulation voltages (AWL) derived from these replicas, ART detects when the data degradation in DRDPC causes the analog output to deviate by more than 0.5 LSB from the SRDPC reference. At this threshold, a refresh enable signal is triggered, initiating a targeted refresh operation. To ensure conservative estimation, the DRDPC is intentionally designed with reduced capacitance, making it more sensitive to leakage. This setup enables accurate, corner-aware tracking without external sensors, achieving up to 61% refresh power reduction with only 1.56% area overhead. 2025-07-04 Address Buffer • The row decoder is designed to process a 9-bit address input, selecting one out of 512 rows. To minimize decoding latency and area overhead, the address is divided across multiple logic stages, enabling efficient one-hot decoding. This hierarchical structure reduces fan-out and simplifies signal routing, which is critical for large-scale integration. Addressing optimization is particularly important in DRAM-PIM architectures, where frequent switching and tight timing constraints demand fast and energy-efficient row selection. By optimizing the address path, the decoder ensures reliable wordline activation across subarrays without unnecessary delay or power loss, directly contributing to the overall performance and scalability of the system. 2025-07-04 DRAM_PIM Decoder • The row decoder is designed to handle a 9-bit address input, allowing the selection of one out of 512 columns. To control its operation, several global signals are utilized. The Decoder_enable signal ensures that no decoder output is unintentionally activated when no valid address is present, effectively disabling all decoder outputs when needed. The Write/read enable signal determines whether the write word line (WWL) or read word line (RWL) is activated, enabling appropriate access to the cell array. For MAC operations, MAC_enable and MAC_mux signals are used to drive the MAC word line (MWL). Each subarray includes a multiplexer that enables the same cell position across subarrays simultaneously, such as cell<0>, cell<4>, cell<8>, and so on. 2025-07-04 Digital_Post_Accumulator The proposed post-accumulator is used in the MAC operation process, which receives bit-serial input and accumulates the MAC results generated in each cycle by reflecting the bit positions of the 8-bit input activation. This circuit takes a 13-bit MAC result as input, adds it to the result from the previous cycle, and left-shifts the summed result by 1 bit to align with the bit position of the next cycle's input. This process is repeated over 8 cycles, ultimately generating a 20-bit output. The post-accumulator operates with a clock period of 4 ns and a supply voltage of 1.0 V. 2025-07-04 처음으로 이전페이지 2 3 4 5 6 7 8 9 10 11 >다음페이지 마지막으로
