IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(23) Processor Solutions(39) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 140건 현재 페이지 10/35 최신 순 오래된 순 파워업 감지회로 The Power-On Reset (POR) circuit is an analog IP designed to generate a reliable reset signal during both power-up and power-down sequences. Implemented in a standard CMOS process, this IP ensures that digital and mixed-signal systems remain in a known safe state until the supply voltage reaches a stable threshold, enabling robust startup behavior across a wide range of conditions. The POR IP is composed entirely of analog building blocks and requires no external clock, biasing, or digital input control. It receives a single analog input (VDD) and outputs a digital reset signal (VOUT). The core signal path consists of a voltage divider, temperature compensator, and reset signal generator. The voltage divider provides a scalable reference for comparison, while the temperature compensator suppresses variations in threshold voltage due to temperature changes. The reset signal generator includes a carefully sized inverter chain with embedded hysteresis for stable switching behavior. The circuit is designed to generate the reset signal when the supply voltage crosses a defined rising threshold during power-up, and to reassert the reset during power-down when the voltage drops below a falling threshold. The built-in hysteresis ensures noise immunity and eliminates false resets due to supply ripples or slow ramping. 2025-07-02 Voltage reference This Bandgap Reference (BGR) IP is an ultra-low-power, sub-1V analog voltage reference generator designed for integration in advanced mixed-signal SoCs. It generates temperature- and supply-stable reference voltage suitable for low-voltage, low-power applications such as biomedical front ends, IoT sensor nodes, and DRAM PIM systems. The IP operates entirely in the analog domain, taking a single supply voltage as input and producing a precise reference voltage output. It does not require any digital control interface. Internally, it includes a proportional-to-absolute-temperature (PTAT) current generator, a complementary-to-absolute-temperature (CTAT) reference path, and a high-gain two-stage operational amplifier. A dedicated startup circuit ensures reliable initialization under all process, voltage, and temperature conditions. The feedback structure enhances loop stability and provides strong immunity against supply and temperature variations. The design emphasizes high PSRR and a low temperature coefficient, supporting robust performance in environments with fluctuating supply and ambient conditions. The IP is implemented in a standard CMOS process and features a compact layout area, making it well-suited for highly integrated, battery-powered systems and always-on analog blocks. 2025-07-02 Supply regulator The “Supply regulator” is a fully integrated NMOS-based linear regulator designed for ultra-low input voltage operation. The core of the LDO comprises an NMOS pass transistor, an error amplifier (EA), and a charge pump-based gate voltage booster known as the invert-phase synchronized self-oscillating charge pump (I-SOCP). This architecture enables the system to regulate output voltage with a dropout voltage well below the threshold voltage of the pass transistor, even under supply voltages below 1V. The NMOS pass transistor is driven by a gate voltage (VG) generated by the I-SOCP, which operates without an external clock and maintains VG above the input voltage. This elevated VG allows the NMOS transistor to enter the triode region and minimize the dropout voltage. Simultaneously, the I-SOCP output is used as the supply for the EA, thereby ensuring adequate headroom and linear regulation even under sub-1V input conditions. Unlike conventional LDOs with step-up charge pumps, the proposed architecture does not require large flying or output capacitors. Instead, the gate capacitance of the pass transistor is used directly, reducing area and power overhead. The I-SOCP operates in a self-oscillating and phase-synchronized manner, which improves the voltage boosting capability by enabling both rising and falling edge operations of internal nodes. This NMOS LDO is ideal for low-power SoC platforms where minimal dropout and high efficiency under low voltage supplies are critical. Its fully analog regulation, self-oscillating clock generation, and compact capacitor-less boosting structure make it suitable for integration in advanced battery-powered systems. 2025-07-02 Hybrid D-FF The Hybrid D Flip-Flop (Hybrid D-FF) is a compact, low-power, fully digital sequential logic IP designed for near-threshold computing (NTC) systems. It is implemented in a 28 nm low-power CMOS process and operates reliably down to 0.25 V, making it ideal for energy-efficient SoCs and low-voltage digital platforms. The flip-flop is fully compatible with standard digital design flows and require no external biasing or control signals beyond the clock (CK) and data (D) inputs. This flip-flop features a hybrid architecture that combines the robustness of transmission-gate flip-flops (TGFF) with the speed and simplicity of true single-phase clock (TSPC) logic. The design utilizes both feedback and feedforward paths to improve data stability and reduce output delays. The input (D) is sampled on the rising edge of the clock (CK), and the output (Q) is updated accordingly. No asynchronous set or reset is included, allowing for minimal area and power overhead. Structurally, the Hybrid-FF is composed of a small number of transistors (20 total, including clock inverters), a split TSPC-style latch, and a compact clocking scheme that ensures full voltage transitions without contention. The latch stage employs a feedback loop for stability and a carefully tuned capacitance path to minimize clock-to-Q delay. Architecture eliminates the Vth drop issue commonly found in TSPC designs and ensures full-swing outputs under low voltage. 2025-07-02 처음으로 이전페이지 5 6 7 8 9 10 11 12 13 14 >다음페이지 마지막으로
