IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(22) Processor Solutions(38) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 138건 현재 페이지 6/35 최신 순 오래된 순 AER (Address-Event Representation) IP (차세대지능형반도체사업단) 비동기 뉴럴 스파이크 전송을 위하여 Req / Ack 기반의 4-phase handshaking protocol 을 채택한 통신 회로로서 계층 구조에 기반하여 다수의 neural block 선택 및 다수의 입출력 뉴럴 스파이크 전송 처리 기능을 수행하는 IP 2026-01-28 DRAM Redundancy • The proposed redundancy mechanism is designed to ensure reliable MAC operations in analog PIM macros by addressing MDRT (MAC Data Retention Time) failures, which are not covered by conventional techniques. A Spare_enable signal activates the redundancy controller only when a failure address is detected. The Decoder (DEC) generates MUX_select signals, which determine whether each MAC output comes from the core row or the spare row. Under normal operation, all MUXes pass the original core outputs to the adder. When a failure address is matched, the corresponding MUX switches its input to the spare MAC row, and the Spare_bit logic ensures that only the failed row is redirected. This allows accurate delivery of MAC results with proper bit-position alignment, preserving output integrity even in the presence of retention failures. In contrast, previous methods suffer from several limitations: • Conventional redundancy schemes such as spare row/column replacement or I/O line shifting focus only on CDRT (Cell Data Retention Time) failures and cannot detect or repair MDRT-related issues. • In bit-position-sensitive MAC operations, shifting-based repair corrupts the alignment between MAC outputs and digital bit positions, leading to incorrect accumulation results. • Previous methods rely on external failure maps and lack the ability to dynamically reflect MAC-specific degradation patterns within the compute path. Therefore, the proposed approach provides in-situ MDRT repair with bit-position fidelity, overcoming both detection and precision limitations of earlier techniques. 2025-07-04 DRAM Refresh Circuit • The Adaptive Refresh Tracking (ART) mechanism dynamically adjusts refresh timing based on real-time retention behavior, minimizing unnecessary refresh operations and power overhead. ART utilizes two types of replica eDRAM cells: a Static Replica DPC (SRDPC) and a Dynamic Replica DPC (DRDPC). The SRDPC is isolated from leakage effects and provides a stable voltage reference, while the DRDPC mimics the leakage characteristics of real cells in the array. By comparing the wordline accumulation voltages (AWL) derived from these replicas, ART detects when the data degradation in DRDPC causes the analog output to deviate by more than 0.5 LSB from the SRDPC reference. At this threshold, a refresh enable signal is triggered, initiating a targeted refresh operation. To ensure conservative estimation, the DRDPC is intentionally designed with reduced capacitance, making it more sensitive to leakage. This setup enables accurate, corner-aware tracking without external sensors, achieving up to 61% refresh power reduction with only 1.56% area overhead. 2025-07-04 Address Buffer • The row decoder is designed to process a 9-bit address input, selecting one out of 512 rows. To minimize decoding latency and area overhead, the address is divided across multiple logic stages, enabling efficient one-hot decoding. This hierarchical structure reduces fan-out and simplifies signal routing, which is critical for large-scale integration. Addressing optimization is particularly important in DRAM-PIM architectures, where frequent switching and tight timing constraints demand fast and energy-efficient row selection. By optimizing the address path, the decoder ensures reliable wordline activation across subarrays without unnecessary delay or power loss, directly contributing to the overall performance and scalability of the system. 2025-07-04 처음으로 이전페이지 1 2 3 4 5 6 7 8 9 10 >다음페이지 마지막으로
