IP 검색 Category Analog & Mixed Signal(14) Memory Controller & PHY(0) Memory & Logic Library(9) Interface Controller & PHY(0) Processor Solutions(3) Arithmetic & Mathematic IP(1) Peripheral(1) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(1) Other(83) Verification IP(9) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 119건 현재 페이지 6/30 BBCDR for multi-rate high speed SerDes receiver (차세대지능형반도체사업단) · PCIe interface system 지원 가능한 Multi-rate BBCDR 2024-08-29 BF16, FP32 복합 데이터 타입 병렬 연산기 (차세대지능형반도체사업단) · 부동소수점 복합 데이터 타입(BF16, FP32) 연산을 가속하는 외적 기반 행렬곱 병렬 연산기 2024-08-29 BL Sense Amplifier • The proposed sense amplifier, named the Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier (DISA), is a monolithic, low-power, high-speed sensing solution for DRAMs fabricated in 28 nm CMOS technology. It employs a dual-input stacked inverter architecture with bit-line (BL) switches and a single-ended structure to minimize area, power, and timing overhead. Unlike conventional bit-line sense amplifiers (BLSAs) that rely on differential coupling capacitors and require a dedicated offset-cancellation (OC) phase, DISA performs offset cancellation and charge sharing simultaneously. This eliminates the timing penalty from OC time and enables the fastest sensing operation, achieving sensing times of less than 9 ns at 0.7 V and less than 8 ns at 0.8 V, defined as the time when BL and BLB reach 80% and 20% of VDD, respectively. Thanks to its single-ended topology and use of only one coupling capacitor, DISA occupies the smallest area among compared designs and supports high-density DRAM layouts with sub-50 nm bit-line pitch. The dual-input stacked inverter enhances gain by using stacked transistors operating in the linear region, significantly reducing static current in both the OC and main sensing phases. In addition, direct BL connection to the IN node improves noise immunity by avoiding floating nodes and ensuring robust sensing even under process scaling and voltage reduction. Overall, DISA demonstrates superior energy efficiency, achieving the lowest measured sensing energy of 5.8 fJ/cycle/bit, and supports low-voltage operation down to 0.55 V, making it highly suitable for advanced low-power DRAM applications. 2025-07-04 Camera System (차세대지능형반도체사업단) · N-Dolphin의 Video Input Interface 2024-08-29 처음으로 이전페이지 1 2 3 4 5 6 7 8 9 10 >다음페이지 마지막으로
