IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(23) Processor Solutions(39) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 140건 현재 페이지 6/35 최신 순 오래된 순 Vector Processing Unit (VPU) (차세대지능형반도체사업단) AI 가속기 NPU의 핵심 연산 유닛. SIMD 방식을 기반으로 bf16 데이터 타입의 벡터 연산 수행. SIMD 방식을 기반으로 bf16 데이터 타입의 벡터 연산 수행. 2026-01-29 Flexi-NPU (차세대지능형반도체사업단) bfloat16(BF16) 정밀도의 32-way 병렬 Adder-Tree 구조를 갖춘 행렬곱(Matrix Multiplication) 가속 유닛(IP) 2026-01-29 AER (Address-Event Representation) IP (차세대지능형반도체사업단) 비동기 뉴럴 스파이크 전송을 위하여 Req / Ack 기반의 4-phase handshaking protocol 을 채택한 통신 회로로서 계층 구조에 기반하여 다수의 neural block 선택 및 다수의 입출력 뉴럴 스파이크 전송 처리 기능을 수행하는 IP 2026-01-28 DRAM Redundancy • The proposed redundancy mechanism is designed to ensure reliable MAC operations in analog PIM macros by addressing MDRT (MAC Data Retention Time) failures, which are not covered by conventional techniques. A Spare_enable signal activates the redundancy controller only when a failure address is detected. The Decoder (DEC) generates MUX_select signals, which determine whether each MAC output comes from the core row or the spare row. Under normal operation, all MUXes pass the original core outputs to the adder. When a failure address is matched, the corresponding MUX switches its input to the spare MAC row, and the Spare_bit logic ensures that only the failed row is redirected. This allows accurate delivery of MAC results with proper bit-position alignment, preserving output integrity even in the presence of retention failures. In contrast, previous methods suffer from several limitations: • Conventional redundancy schemes such as spare row/column replacement or I/O line shifting focus only on CDRT (Cell Data Retention Time) failures and cannot detect or repair MDRT-related issues. • In bit-position-sensitive MAC operations, shifting-based repair corrupts the alignment between MAC outputs and digital bit positions, leading to incorrect accumulation results. • Previous methods rely on external failure maps and lack the ability to dynamically reflect MAC-specific degradation patterns within the compute path. Therefore, the proposed approach provides in-situ MDRT repair with bit-position fidelity, overcoming both detection and precision limitations of earlier techniques. 2025-07-04 처음으로 이전페이지 1 2 3 4 5 6 7 8 9 10 >다음페이지 마지막으로
