IP 검색 Category Analog & Mixed Signal(14) Memory Controller & PHY(0) Memory & Logic Library(9) Interface Controller & PHY(0) Processor Solutions(3) Arithmetic & Mathematic IP(1) Peripheral(1) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(1) Other(83) Verification IP(9) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 119건 현재 페이지 30/30 인공지능 프로세서의 메모리 요구 특성에 맞는 스케줄러 (차세대지능형반도체사업단) 3종 메모리 (HBM2, DDR4, SRAM)로 구성된 이종 메모리 시스템을 효율적으로 사용할 수 있는 스케줄러 2024-08-29 준지도학습 가속기 (Semi-supervised Learning Accelerator) (차세대지능형반도체사업단) · ‘자가 학습’의 핵심/요소 기능인 준지도학습 기능의 고속/저전력처리를 위한 H/W 가속기 IP 2024-08-29 파워업 감지회로 The Power-On Reset (POR) circuit is an analog IP designed to generate a reliable reset signal during both power-up and power-down sequences. Implemented in a standard CMOS process, this IP ensures that digital and mixed-signal systems remain in a known safe state until the supply voltage reaches a stable threshold, enabling robust startup behavior across a wide range of conditions. The POR IP is composed entirely of analog building blocks and requires no external clock, biasing, or digital input control. It receives a single analog input (VDD) and outputs a digital reset signal (VOUT). The core signal path consists of a voltage divider, temperature compensator, and reset signal generator. The voltage divider provides a scalable reference for comparison, while the temperature compensator suppresses variations in threshold voltage due to temperature changes. The reset signal generator includes a carefully sized inverter chain with embedded hysteresis for stable switching behavior. The circuit is designed to generate the reset signal when the supply voltage crosses a defined rising threshold during power-up, and to reassert the reset during power-down when the voltage drops below a falling threshold. The built-in hysteresis ensures noise immunity and eliminates false resets due to supply ripples or slow ramping. 2025-07-02 처음으로 이전페이지 21 22 23 24 25 26 27 28 29 30 >다음페이지 마지막으로
