IP 검색 Category Analog & Mixed Signal(14) Memory Controller & PHY(0) Memory & Logic Library(9) Interface Controller & PHY(0) Processor Solutions(3) Arithmetic & Mathematic IP(1) Peripheral(1) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(1) Other(83) Verification IP(9) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 119건 현재 페이지 26/30 Single-to-differential amplifier (차세대지능형반도체사업단) · Strobe signal 이 single-ended input 으로 인가될 경우 differential signal 로 변환하기 위한 block 2024-08-29 SPI Controller (차세대지능형반도체사업단) · N-Dolphin의 SPI interface 2024-08-29 Supply regulator The “Supply regulator” is a fully integrated NMOS-based linear regulator designed for ultra-low input voltage operation. The core of the LDO comprises an NMOS pass transistor, an error amplifier (EA), and a charge pump-based gate voltage booster known as the invert-phase synchronized self-oscillating charge pump (I-SOCP). This architecture enables the system to regulate output voltage with a dropout voltage well below the threshold voltage of the pass transistor, even under supply voltages below 1V. The NMOS pass transistor is driven by a gate voltage (VG) generated by the I-SOCP, which operates without an external clock and maintains VG above the input voltage. This elevated VG allows the NMOS transistor to enter the triode region and minimize the dropout voltage. Simultaneously, the I-SOCP output is used as the supply for the EA, thereby ensuring adequate headroom and linear regulation even under sub-1V input conditions. Unlike conventional LDOs with step-up charge pumps, the proposed architecture does not require large flying or output capacitors. Instead, the gate capacitance of the pass transistor is used directly, reducing area and power overhead. The I-SOCP operates in a self-oscillating and phase-synchronized manner, which improves the voltage boosting capability by enabling both rising and falling edge operations of internal nodes. This NMOS LDO is ideal for low-power SoC platforms where minimal dropout and high efficiency under low voltage supplies are critical. Its fully analog regulation, self-oscillating clock generation, and compact capacitor-less boosting structure make it suitable for integration in advanced battery-powered systems. 2025-07-02 Tensor CACHE (TCACHE) (차세대지능형반도체사업단) · 서버 NPU 연산을 위한 입출력 data를 저장하는 memory · 서버 NPU Subblock IP 2024-08-29 처음으로 이전페이지 21 22 23 24 25 26 27 28 29 30 >다음페이지 마지막으로