IP 검색 Category Analog & Mixed Signal(14) Memory Controller & PHY(0) Memory & Logic Library(9) Interface Controller & PHY(0) Processor Solutions(3) Arithmetic & Mathematic IP(1) Peripheral(1) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(1) Other(83) Verification IP(9) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 119건 현재 페이지 27/30 Tensor DMA (TDMA) (차세대지능형반도체사업단) · NPU Tensor Cache (TCACHE)와 External Memory사이의 data transfer를 위한 장치. Data transfer와 함께 layout 변경 기능을 지원 · 서버 NPU Subblock IP 2024-08-29 Time-to-Digital Converter (차세대지능형반도체사업단) · All-Digital PLL 에서의 Phase 차이를 digital domain으로 측정 및 변환 가능한 TDC 2024-08-29 Unity-gain buffer The "Unity-Gain Buffer" is a low-power, fully differential analog buffer IP designed for high-speed, low-distortion applications requiring voltage following with minimal offset and excellent linearity. The IP is composed of a differential-input, single-ended-output operational amplifier configured in a unity-gain feedback topology. Users must connect ‘Analog op-amp’ IP’s ports both VINN and VOUT together to use ‘Unity-Gain Buffer’. The analog IP receives an input signal and outputs a single-ended signal that follows input signal. Internally, the design includes a compensation network optimized for unity-gain stability, ensuring no oscillation. Structurally, the amplifier consists of a PMOS input differential pair with active current mirror loads, followed by a single-ended gain stage that converts the differential signal to a single-ended output. A Miller or feedforward compensation path is included to guarantee sufficient phase margin in unity-gain buffer configuration and other closed-loop applications. The buffer is designed with the feedback network determines the effective gain, while the amplifier ensures linearity and stability. No digital inputs or control interfaces are required, and the amplifier responds continuously to analog input variations. The IP Implemented in a 28 nm CMOS low power process. 2025-07-02 Versatile Pooling Unit (차세대지능형반도체사업단) · 심층강화학습에 필요한 행렬곱 연산을 추론, 오차 역전파 및 가중치 업데이트를 에너지 효율적으로 가속하기위한 유닛 (IP) · NPU – (Core - PE Array – PE), (DMEM – L2 Cache, ADAM Logic Unit) 2024-08-30 처음으로 이전페이지 21 22 23 24 25 26 27 28 29 30 >다음페이지 마지막으로
