IP 검색 Category Analog & Mixed Signal(14) Memory Controller & PHY(0) Memory & Logic Library(9) Interface Controller & PHY(0) Processor Solutions(3) Arithmetic & Mathematic IP(1) Peripheral(1) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(1) Other(83) Verification IP(9) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 119건 현재 페이지 23/30 PE Array for CNN (차세대지능형반도체사업단) · CNN(Convolutional Neural Network) 처리를 위한 최적화된 array 구조 2024-08-29 PLL-based clock generator for PIM · The frequency synthesizer generates a range of frequencies from a single reference frequency, which usually comes from a crystal oscillator. Frequency synthesizers are one of the most critical building blocks in modern electronic devices, such as mobile telephones, laptops, televisions, radiotelephones, satellite communications, GPS systems, etc. One of the popular types of frequency synthesizers is a phase-locked loop (PLL). In Processing-in-Memory (PIM), PLL will be designed and used to synchronize a clock inside the PIM. 2024-07-24 Repeater Chain The Repeater Chain IP is a mixed-signal, high-speed, low-power signal conditioning block designed to restore signal quality across long on-chip interconnects. It consists of a cascaded buffer/inverter architecture that compensates for RC-induced delay and waveform degradation, ensuring clean and reliable digital signal propagation over extended wire lengths. The core employs a multi-stage structure of optimally sized CMOS repeaters, each regenerating the signal and sharpening its transition edges. Input and output are both standard digital logic levels, with the output exhibiting enhanced edge rate and minimized delay skew. The number and placement of repeater stages are tuned based on wire length, capacitive loading, and timing constraints. To support robust operation under process, voltage, and temperature (PVT) variations, the IP optionally integrates control logic for dynamic drive strength adaptation. This ensures consistent performance across corner cases without requiring external calibration. Designed for integration in global SoC routing paths, clock distribution trees, and high-speed data buses, the Repeater Chain IP provides an essential solution for maintaining signal integrity and timing reliability in advanced digital systems. Figure 1 shows the functional block diagram of the repeater chain, including the parasitic load capacitance from the metal line. Implemented in a 28nm standard CMOS process with minimal area and power overhead, it is well suited for power-conscious, high-performance applications. 2025-06-24 Resistance Implementation in Phase-Change Memory Precise resistance control in Phase-Change Random Access Memory (PRAM) by adjusting pulse parameters such as amplitude, trailing edge, and delay. 2025-03-10 처음으로 이전페이지 18 19 20 21 22 23 24 25 26 27 >다음페이지 마지막으로
