IP 검색 Category Analog & Mixed Signal(14) Memory Controller & PHY(0) Memory & Logic Library(9) Interface Controller & PHY(0) Processor Solutions(3) Arithmetic & Mathematic IP(1) Peripheral(1) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(1) Other(83) Verification IP(9) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 119건 현재 페이지 18/30 Hybrid D-FF The Hybrid D Flip-Flop (Hybrid D-FF) is a compact, low-power, fully digital sequential logic IP designed for near-threshold computing (NTC) systems. It is implemented in a 28 nm low-power CMOS process and operates reliably down to 0.25 V, making it ideal for energy-efficient SoCs and low-voltage digital platforms. The flip-flop is fully compatible with standard digital design flows and require no external biasing or control signals beyond the clock (CK) and data (D) inputs. This flip-flop features a hybrid architecture that combines the robustness of transmission-gate flip-flops (TGFF) with the speed and simplicity of true single-phase clock (TSPC) logic. The design utilizes both feedback and feedforward paths to improve data stability and reduce output delays. The input (D) is sampled on the rising edge of the clock (CK), and the output (Q) is updated accordingly. No asynchronous set or reset is included, allowing for minimal area and power overhead. Structurally, the Hybrid-FF is composed of a small number of transistors (20 total, including clock inverters), a split TSPC-style latch, and a compact clocking scheme that ensures full voltage transitions without contention. The latch stage employs a feedback loop for stability and a carefully tuned capacitance path to minimize clock-to-Q delay. Architecture eliminates the Vth drop issue commonly found in TSPC designs and ensures full-swing outputs under low voltage. 2025-07-02 I/O Sense Amplifier • The proposed sense amplifier, named the Static Current-Free Pre-Sensing IO Sense Amplifier (SCFP-IOSA), is a high-speed, low-power sensing solution for DRAM global I/O in 28 nm CMOS technology. It employs a direct input transfer architecture using a single coupling capacitor (CC) and introduces a static current-free pre-sensing technique to minimize offset voltage (VOS), area, and energy overhead. Unlike conventional offset cancellation (OC)-based I/O sense amplifiers, which suffer from input voltage attenuation, large area due to dual CCs, and static current during sensing, SCFP-IOSA eliminates attenuation by directly transferring the input differential voltage (ΔVGIO) and avoids static current using exponential RC pre-amplification. The proposed design separates ΔVGIO generation and sensing by GIO switches, allowing simultaneous offset cancellation and input development. This reduces sensing time overhead and enables a fast sensing time of 3.75 ns, with 2.15 μW power consumption, and 10.28 μm² area, achieving 3× lower σVOS, 2.9× lower power, and 4.46× smaller area compared to state-of-the-art OC-IOSA. Moreover, it shows robust sensing yield even in noisy conditions, and maintains performance at low supply voltages. These characteristics make SCFP-IOSA highly suitable for next-generation low-voltage, high-density DRAM applications, particularly in 1Ynm-class or beyond. 2025-07-04 Input Clock Buffer This digital buffer takes CMOS level input and generates CMOS level output. It achieves high power efficiency, low rise-fall skew, and moderate noise level. Figure 1 shows a functional block diagram of the buffer. Four inputs (in0 ~ in3) are respectively buffered. 2025-06-24 L2H(High to low shifter) (차세대지능형반도체사업단) · HBM의 Subblock IP · FPGA로 데이터 송신을 위한 회로 2024-08-29 처음으로 이전페이지 13 14 15 16 17 18 19 20 21 22 >다음페이지 마지막으로
