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Input Clock Buffer

This digital buffer takes CMOS level input and generates CMOS level output. It achieves high power efficiency, low rise-fall skew, and moderate noise level. Figure 1 shows a functional block diagram of the buffer. Four inputs (in0 ~ in3) are respectively buffered.

Feature

· • Digital buffer having four inputs and four outputs.
· • Output frequency up to 10 GHz.
· • Supply voltage: 0.9 V to 1.1 V
· • Propagation delay: < 30 ps (Fan-out 4 load)
· • Industrial temperature range: –40°C to 125°C
· • Input capacitance: 1 fF for each input
· • Core area: 5.2 um x 2.82 um
· • Power Consumption (NN corner)
· - 36.5 uW at 1 GHz
· - 365.0 uW at 10 GHz

Application

· • Digital buffer
· • Clock distribution

Business Area

Wireline Communication

Category

Memory & Logic Library > I/O Library

Tech Specs

IP Name :
Input Clock Buffer
Provider :
SeongHwan Cho
Foundry :
SAMSUNG
Technology :
28nm

Deliverables

· Schematic netlist & testbench

Validation Status

· Simulation-proven

Availability

Samsung 28nm Only

Benefits

Datasheet

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