IP 검색 Category Analog & Mixed Signal(14) Memory Controller & PHY(0) Memory & Logic Library(9) Interface Controller & PHY(0) Processor Solutions(3) Arithmetic & Mathematic IP(1) Peripheral(1) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(1) Other(83) Verification IP(9) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 119건 현재 페이지 28/30 Voltage comparator The ‘Voltage comparator’ is an analog IP block that accepts two analog voltage inputs: INP (positive input) and INN (negative input). It evaluates the polarity of the differential input voltage (INP - INN) and produces a differential digital output through OUTP and OUTN nodes. The comparison process is gated by a digital control signal, EN, which acts as a clock or trigger. Upon receiving a rising edge or high-level pulse at EN, the comparator enters an evaluation phase, internally activates the decision circuitry, and latches the result based on the instantaneous differential input. The output is inversed signal versus EN. The output settles quickly to a valid logic level using an internal regenerative latch, providing robust and noise-immune decisions even under small input differences. Fabricated in a 28nm CMOS Low power process. 2025-07-02 Voltage reference This Bandgap Reference (BGR) IP is an ultra-low-power, sub-1V analog voltage reference generator designed for integration in advanced mixed-signal SoCs. It generates temperature- and supply-stable reference voltage suitable for low-voltage, low-power applications such as biomedical front ends, IoT sensor nodes, and DRAM PIM systems. The IP operates entirely in the analog domain, taking a single supply voltage as input and producing a precise reference voltage output. It does not require any digital control interface. Internally, it includes a proportional-to-absolute-temperature (PTAT) current generator, a complementary-to-absolute-temperature (CTAT) reference path, and a high-gain two-stage operational amplifier. A dedicated startup circuit ensures reliable initialization under all process, voltage, and temperature conditions. The feedback structure enhances loop stability and provides strong immunity against supply and temperature variations. The design emphasizes high PSRR and a low temperature coefficient, supporting robust performance in environments with fluctuating supply and ambient conditions. The IP is implemented in a standard CMOS process and features a compact layout area, making it well-suited for highly integrated, battery-powered systems and always-on analog blocks. 2025-07-02 Voltage-to-Time Converter The Voltage-to-Time Converter (VTC) is a high-speed, low-power, and variation-tolerant IP which generates a time-domain output pulse PVTC proportional to the voltage difference between two analog voltage inputs VIN and VREF (Figure 1). The VTC generates a timing pulse based on the delay caused by charging a capacitor from VIN until it reaches an inverter’s threshold. By subtracting a pulse proportional to VREF from this timing pulse, a final output pulse PVTC proportional to VIN – VREF is obtained. The IP includes a power-saving mode enabled via specific clock phase state, significantly reducing power consumption when inactive. Fabricated in a 28 nm CMOS process and occupying only 28 μm² of core area, the VTC is ideal for integration into power-sensitive and space-constrained mixed-signal systems. Designed for robustness across varying environmental conditions, the VTC offers excellent tolerance to supply voltage and temperature fluctuations, with output pulse variation maintained within tens of picoseconds across the full operating range. It supports high-frequency operation exceeding 10 MHz, making it suitable for fast, event-driven applications. 2025-06-24 Write-with-Feedback Circuit The Write-with-Feedback Circuit is an analog amplifier IP designed for use in read and write operations of analog memory systems. During these operations, a source follower typically connected to the back end of the storage capacitor introduces a threshold voltage (Vth) drop, resulting in a mismatch between the written and read voltage levels. This mismatch can cause distortion in the read-out value, degrading memory accuracy. To address this issue, the amplifier enables a write-with-feedback loop that virtually shorts the write input and the memory’s output node. By enforcing this virtual short condition, the amplifier compensates for the Vth drop during the write operation, ensuring that the intended voltage is properly stored in the analog memory and accurately retrieved during the read phase. The amplifier is implemented using a 5-transistor operational amplifier (5-tr opamp) topology, in Samsung’s 28 nm LPP CMOS process using analog low-Vth (anglvt) devices. 2025-06-24 처음으로 이전페이지 21 22 23 24 25 26 27 28 29 30 >다음페이지 마지막으로
