• The proposed sense amplifier, named the Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier (DISA), is a monolithic, low-power, high-speed sensing solution for DRAMs fabricated in 28 nm CMOS technology. It employs a dual-input stacked inverter architecture with bit-line (BL) switches and a single-ended structure to minimize area, power, and timing overhead. Unlike conventional bit-line sense amplifiers (BLSAs) that rely on differential coupling capacitors and require a dedicated offset-cancellation (OC) phase, DISA performs offset cancellation and charge sharing simultaneously. This eliminates the timing penalty from OC time and enables the fastest sensing operation, achieving sensing times of less than 9 ns at 0.7 V and less than 8 ns at 0.8 V, defined as the time when BL and BLB reach 80% and 20% of V_DD, respectively. Thanks to its single-ended topology and use of only one coupling capacitor, DISA occupies the smallest area among compared designs and supports high-density DRAM layouts with sub-50 nm bit-line pitch. The dual-input stacked inverter enhances gain by using stacked transistors operating in the linear region, significantly reducing static current in both the OC and main sensing phases. In addition, direct BL connection to the IN node improves noise immunity by avoiding floating nodes and ensuring robust sensing even under process scaling and voltage reduction. Overall, DISA demonstrates superior energy efficiency, achieving the lowest measured sensing energy of 5.8 fJ/cycle/bit, and supports low-voltage operation down to 0.55 V, making it highly suitable for advanced low-power DRAM applications.