Feature
· • CML2CMOS: Current-mode-logic (CML) to CMOS-level conversion
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• Low-swing differential CML input to full-swing CMOS output
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• CMOS-compatible rail-to-rail outputs
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• Designed in 28 nm CMOS Process
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• Supports quadrature-phase outputs with differential format: ICLK, QCLK, IBCLK, QBCLK
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• Two-stage differential signaling
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• Input support: single-ended swing ≥ 40 mV (typ. 300 mV)
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• Supply voltage range: 0.9 V to 1.02 V
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• Typical bandwidth: 1.6 GHz (Max. 1.87 GHz)
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• Tunability via external analog bias (VB)
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• Power consumption: 89.4 µW @ 1.0 V, 1.6 GHz, 300 mVpp input swing
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• Input common mode range: 0.25V to 0.65V
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• Operating temperature range: -40 - 125 ℃
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• 0.004mm2 Core Area
Application
· • CML-to-CMOS level conversion for clock distribution networks
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• CML clock reception and CMOS regene
Deliverables
· Schematic netlist & testbench