The CML2CMOS is a compact converter IP that translates differential current-mode logic (CML) clock signals into full-swing CMOS levels. Fabricated in a 28 nm CMOS process, it supports output clock frequencies up to 1.87 GHz while consuming less than 0.5 mW.
The IP receives differential CML inputs and converts them into CMOS logic outputs using a two-stage architecture. Each stage consists of a current-steering differential pair that performs differential-to-single-ended conversion and is followed by a CMOS inverter buffer. The same structure is duplicated across phases to produce four-phase outputs: ICLK, IBCLK, QCLK, and QBCLK. This ensures matched delay paths and balanced timing across all phases.
The converter supports basic bias-based configurability through an external analog control voltage, “VB”, that sets the tail current of the differential pair. This mechanism allows limited tuning of delay and power characteristics to adapt to different operating conditions.
Designed for robustness and compactness, the CML2CMOS block is suitable for clock signal reception and level translation in differential clock distribution paths such as memory interfaces, SerDes, and other high-speed clocking architectures.