The CML driver drives two pairs differential CMOS level inputs (inIp & inIn, inQp & inQn) to two pairs of differential current-mode logic outputs (Ioutp & Ioutn, Qoutp & Qoutn) with minimum skew for high speed signal distribution. The CML driver is specifically designed for a clock distribution network for high speed signaling. A bias current is necessary to bias the current sources in the CML driver. The biasing circuitry can be amortized over multiple drivers to minimize the overhead. The device operates from 0.9-V to 1.1-V supply environment and is characterized from –40°C to 125°C. The CML driver employs a fully differential structure in order to maximize the rejection capabilities against common-mode noise and power supply noise. The CML driver has been experimentally verified through its application in LPDDR5 DRAM interface.
Feature
· • High-performance CML driver with 2 input pairs and 2 output pairs.
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• Output frequency up to 2 GHz.
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• Supply voltage: 0.9 V to 1.1 V
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• Low additive jitter: 120 fs (rms)
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• Low propagation delay: 36 ps
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• CMOS level inputs
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• Industrial temperature range: –40°C to 125°C
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• Low Input capacitance < 20fF
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• Small core area: 1710 um2
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• Excellent Gain and Phase Matching
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• Low Power Consumption
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- 0.69 mW at 100 MHz
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- 1.02 mW at 1.6 GHz
Application
· • 6.4Gbps Transmitter for LPDDR5 Mobile DRAM
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• High-speed clock distribution network for high-speed
Business Area
Wireline Communication
Category
Memory & Logic Library > I/O Library
Tech Specs
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IP Name :
CML Driver
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Provider :
SeongHwan Cho
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Foundry :
SAMSUNG
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Technology :
28nm
Deliverables
· Schematic netlist & testbench
Validation Status
· Simulation-proven
Availability
Samsung 28nm Only
