• The row decoder is designed to handle a 9-bit address input, allowing the selection of one out of 512 columns. To control its operation, several global signals are utilized. The Decoder_enable signal ensures that no decoder output is unintentionally activated when no valid address is present, effectively disabling all decoder outputs when needed. The Write/read enable signal determines whether the write word line (WWL) or read word line (RWL) is activated, enabling appropriate access to the cell array. For MAC operations, MAC_enable and MAC_mux signals are used to drive the MAC word line (MWL). Each subarray includes a multiplexer that enables the same cell position across subarrays simultaneously, such as cell<0>, cell<4>, cell<8>, and so on.
Feature
· • Multiple word-line activation (128 rows)
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• Multiple bit-line data access (144 columns)
Application
· • Adopted in Samsung 28nm CMOS process based 4T1C DRAM-PIM macro
Business Area
DRAM memory system
Category
Verification IP > Memory > Dram
Tech Specs
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IP Name :
DRAM_PIM Decoder
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Provider :
정성욱 교수님, 김도한
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Foundry :
SAMSUNG
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Technology :
28nm
Deliverables
· Schematic netlist & GDS
Validation Status
· Chip measured
Availability
1Ynm DRAM Technology
