• The proposed redundancy mechanism is designed to ensure reliable MAC operations in analog PIM macros by addressing MDRT (MAC Data Retention Time) failures, which are not covered by conventional techniques. A Spare_enable signal activates the redundancy controller only when a failure address is detected. The Decoder (DEC) generates MUX_select signals, which determine whether each MAC output comes from the core row or the spare row. Under normal operation, all MUXes pass the original core outputs to the adder. When a failure address is matched, the corresponding MUX switches its input to the spare MAC row, and the Spare_bit logic ensures that only the failed row is redirected. This allows accurate delivery of MAC results with proper bit-position alignment, preserving output integrity even in the presence of retention failures.
In contrast, previous methods suffer from several limitations:
• Conventional redundancy schemes such as spare row/column replacement or I/O line shifting focus only on CDRT (Cell Data Retention Time) failures and cannot detect or repair MDRT-related issues.
• In bit-position-sensitive MAC operations, shifting-based repair corrupts the alignment between MAC outputs and digital bit positions, leading to incorrect accumulation results.
• Previous methods rely on external failure maps and lack the ability to dynamically reflect MAC-specific degradation patterns within the compute path.
Therefore, the proposed approach provides in-situ MDRT repair with bit-position fidelity, overcoming both detection and precision limitations of earlier techniques.