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KAIST PIM반도체설계연구센터 이론 교육
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KAIST AI-PIM PIM반도체연구센터

IP 검색

DRAM Refresh Circuit

• The Adaptive Refresh Tracking (ART) mechanism dynamically adjusts refresh timing based on real-time retention behavior, minimizing unnecessary refresh operations and power overhead. ART utilizes two types of replica eDRAM cells: a Static Replica DPC (SRDPC) and a Dynamic Replica DPC (DRDPC). The SRDPC is isolated from leakage effects and provides a stable voltage reference, while the DRDPC mimics the leakage characteristics of real cells in the array.
By comparing the wordline accumulation voltages (AWL) derived from these replicas, ART detects when the data degradation in DRDPC causes the analog output to deviate by more than 0.5 LSB from the SRDPC reference. At this threshold, a refresh enable signal is triggered, initiating a targeted refresh operation. To ensure conservative estimation, the DRDPC is intentionally designed with reduced capacitance, making it more sensitive to leakage. This setup enables accurate, corner-aware tracking without external sensors, achieving up to 61% refresh power reduction with only 1.56% area overhead.

Feature
· • Refresh power reduction: 61% improvement
· • Area overhead: 1.56%
Application
· • Adopted in Samsung 28nm CMOS process based 4T1C DRAM-PIM macro
Business Area
DRAM memory system
Category

Verification IP > Memory > Dram


Tech Specs
  • IP Name :

    DRAM Refresh Circuit

  • Provider :

    정성욱 교수님, 김도한

  • Foundry :

    SAMSUNG

  • Technology :

    28nm

Deliverables
· Schematic netlist & GDS
Validation Status
· Chip measured
Availability
1Ynm DRAM Technology
Functional Diagram
Benefits
·
List