• The row decoder is designed to process a 9-bit address input, selecting one out of 512 rows. To minimize decoding latency and area overhead, the address is divided across multiple logic stages, enabling efficient one-hot decoding. This hierarchical structure reduces fan-out and simplifies signal routing, which is critical for large-scale integration. Addressing optimization is particularly important in DRAM-PIM architectures, where frequent switching and tight timing constraints demand fast and energy-efficient row selection. By optimizing the address path, the decoder ensures reliable wordline activation across subarrays without unnecessary delay or power loss, directly contributing to the overall performance and scalability of the system.
Feature
· • Address optimization for multiple word-line used in MAC mode
Application
· • Adopted in Samsung 28nm CMOS process based 4T1C DRAM-PIM macro
Business Area
DRAM memory system
Category
Verification IP > Memory > Dram
Tech Specs
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IP Name :
Address Buffer
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Provider :
정성욱 교수님, 김도한
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Foundry :
SAMSUNG
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Technology :
28nm
Deliverables
· Schematic netlist & GDS
Validation Status
· Chip measured
Availability
1Ynm DRAM Technology