• The row decoder is designed to process a 9-bit address input, selecting one out of 512 rows. To minimize decoding latency and area overhead, the address is divided across multiple logic stages, enabling efficient one-hot decoding. This hierarchical structure reduces fan-out and simplifies signal routing, which is critical for large-scale integration. Addressing optimization is particularly important in DRAM-PIM architectures, where frequent switching and tight timing constraints demand fast and energy-efficient row selection. By optimizing the address path, the decoder ensures reliable wordline activation across subarrays without unnecessary delay or power loss, directly contributing to the overall performance and scalability of the system.