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IP 검색

Capacitive Memory Unit-Cell

The analog memory stores data using a 1T1C(SWR , Cmem) structure, similar to that of DRAM. To prevent data destruction during read operations, the write and read ports are physically separated. A storage capacitor is placed between these ports, and a source-follower buffer is used to sense the stored voltage without disturbing it. The source-follower consists of an NMOS(M1) input transistor and a current source(M2) biased by an analog voltage(VB). To enhance throughput by 3×, three read switches(SRD0, SRD1, SRD2) are connected to the output of the source-follower. The circuit operates from a 0.9 V to 1.1 V supply and supports an input voltage range of 0.2 V to 0.8 V. It functions reliably over a –20 °C to 85 °C temperature range and can be effectively used in energy-efficient analog in-memory computing (IMC) applications.

Feature
· • Supply voltage: 0.9 V to 1.1 V
· • temperature range: –20°C to 85°C
· • Core size: 1.0 μm × 1.3 μm (in Samsung 28 nm LPP)
· • Input voltage: 0.2 V to 0.8 V
· • Write settle time (99%): 0.6 ns (typ.)
· • Read settle time (99%): 71.9 ns (typ.)
· • Dynamic energy per access: 2.7 fJ (typ.)
· • Retention time: 3.55 μs (typ.), >47 μs (max.)
· • Output sensitivity to supply voltage: 106 mV/V
· • Output sensitivity to temperature: –5.5 mV/°C
· • 3× read ports for enhanced throughput (parallel read)
Application
· • Analog Weight Storage for In-Memory Computing (IMC) / Neural Network Accelerators
Business Area
Low-Power Memory system
Category

Memory & Logic Library > Embedded Memories


Tech Specs
  • IP Name :

    Capacitive Memory Unit-Cell

  • Provider :

    SeongHwan Cho

  • Foundry :

    SAMSUNG

  • Technology :

    28nm

Deliverables
· Schematic netlist & testbench
Validation Status
· Simulation-proven
Availability
Samsung 28nm Only
Benefits
·
List